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? 2010 microchip technology inc. ds21809g-page 1 24aa014/24lc014 device selection table features: single-supply with operation down to 1.7v low-power cmos technology: - 1 ma active current, typical -1 ? a standby current, typical at 5.5v organized as a single block of 128 bytes (128 x 8) hardware write protection for entire array 2-wire serial interface bus, i 2 c? compatible 100 khz and 400 khz clock compatibility page write buffer for up to 16 bytes self-timed write cycle (including auto-erase) 5 ms max. write cycle time address lines allow up to eight devices on bus 1,000,000 erase/write cycles esd protection > 4,000v data retention > 200 years 8-lead pdip, soic, tssop, dfn, tdfn and msop packages 6-lead sot-23 package pb-free and rohs compliant available for extended temperature ranges: description: the microchip technology inc. 24aa014/24lc014 is a 1 kbit serial electrically erasable prom with opera- tion down to 1.7v. the device is organized as a single block of 128 x 8-bit memory with a 2-wire serial inter- face. low-current design permits operation with typical standby and active currents of only 1 ? a and 1 ma, respectively. the device has a page write capability for up to 16 bytes of data. functional address lines allow the connection of up to eight 24aa014/24lc014 devices on the same bus for up to 8 kbits of contiguous eeprom memory. the device is available in the standard 8-pin pdip, 8-pin soic (150 mil), tssop, 2x3 dfn and tdfn and msop packages. the 24aa014/ 24lc014 is also available in the 6-lead sot-23 package. package types block diagram part number v cc range max clock temp. range 24aa014 1.7v - 5.5v 400 khz (1) i 24lc014 2.5v - 5.5v 400 khz i, e note 1: 100 khz for v cc < 2.5v - industrial (i): -40c to +85c - automotive (e) -40c to +125c a0a1 a2 v ss v cc wpscl sda 12 3 4 87 6 5 pdip/soic/tssop/msop a0 a1 a2 v ss wp sclsda v cc 87 6 5 1 2 3 4 sot-23 v cc scl sda v ss a0 a1 dfn/tdfn 1 2 3 4 5 6 i/o control logic memory control logic xdec hv generator eeprom array write-protect circuitry ydec v cc v ss sense amp. r/w control sda scl a0 a1 a2 wp 1k i 2 c ? serial eeprom downloaded from: http:///
24aa014/24lc014 ds21809g-page 2 ? 2010 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc .............................................................................................................................................................................6.5v all inputs and outputs w.r.t. v ss ......................................................................................................... -0.6v to v cc +1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature with power applied ......................................................................................... .......-40c to +125c esd protection on all pins ???????????????????????????????????????????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????? 4 kv table 1-1: dc specifications ? notice : stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc characteristics industrial (i): t a = -40c to +85c, v cc = +1.7v to +5.5v automotive (e): t a = -40c to +125c, v cc = +2.5v to +5.5v param. no. symbol characteristic min. typ. max. units conditions a0, a1, a2, scl, sda and wp pins d1 v ih high-level input voltage 0.7 v cc v d2 v il low-level input voltage 0.3 v cc v0 . 2 v cc for v cc < 2.5v d3 v hys hysteresis of schmitt trigger inputs 0.05 v cc v ( note ) d4 v ol low-level output voltage 0.40 v i ol = 3.0 ma, v cc = 2.5v d5 i li input leakage current 1 ? av in = v ss or v cc d6 i lo output leakage current 1 ? av out = v ss or v cc d7 c in , c out pin capacitance (all inputs/outputs) 1 0p f v cc = 5.5v ( note ) t a = 25c, f clk = 1 mhz d8 i cc write operating current 0.1 3 ma v cc = 5.5v, scl = 400 khz d9 i cc read 0.05 1 ma d10 i ccs standby current 0.01 15 ? a ? a industrial automotive sda = scl = v cc a0, a1, a2, wp = v ss note: this parameter is periodically sampled and not 100% tested. downloaded from: http:///
? 2010 microchip technology inc. ds21809g-page 3 24aa014/24lc014 table 1-2: ac characteristics ac characteristics industrial (i): t a = -40c to +85c, v cc = +1.7v to +5.5v automotive (e): t a = -40c to +125c, v cc = +2.5v to +5.5v param. no. symbol characteristic min. max. units conditions 1f clk clock frequency 100400 khz 1.7v ? v cc < 1.8v 1.8v ? v cc ? 5.5v 2t high clock high time 4000 600 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 5.5v 3t low clock low time 4700 1300 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 5.5v 4t r sda and scl rise time ( note 1 ) 1000 300 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 5.5v 5t f sda and scl fall time ( note 1 ) 1000 300 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 5.5v 6t hd : sta start condition hold time 4000 600 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 5.5v 7t su : sta start condition setup time 4700 600 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 5.5v 8t hd : dat data input hold time 0 ns ( note 2 ) 9t su : dat data input setup time 250 100 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 5.5v 10 t su : sto stop condition setup time 4000 600 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 5.5v 11 t su : wp wp setup time 4000 600 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 5.5v 12 t hd : wp wp hold time 4700 600 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 5.5v 13 t aa output valid from clock ( note 2 ) 3500 900 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 5.5v 14 t buf bus free time: time the bus must be free before a new transmission can start 47001300 ns 1.7v ? v cc < 1.8v 1.8v ? v cc ? 5.5v 16 t sp input filter spike suppression (sda and scl pins) 5 0n s ( note 1 and note 3 ) 17 t wc write cycle time (byte or page) 5 ms 18 endurance 1m cycles 25c, v cc = 5.5v, block mode ( note 4 ) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal mi nimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs, which provide improved noise spike suppression. this eliminates the need for a t i specification for standard operation. 4: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance? model which can be obtained from microchips web site at www.microchip.com. downloaded from: http:///
24aa014/24lc014 ds21809g-page 4 ? 2010 microchip technology inc. figure 1-1: bus timing data (unprotected) (protected) scl sda in sda out wp 5 7 6 16 3 2 89 13 d4 4 10 11 12 14 downloaded from: http:///
? 2010 microchip technology inc. ds21809g-page 5 24aa014/24lc014 2.0 pin descriptions the descriptions of the pins are listed in tab l e 2 - 1 . table 2-1: pin function table 2.1 a0, a1, a2 chip address inputs the a0, a1 and a2 inputs are used by the 24aa014/ 24lc014 for multiple device operation. the levels on these inputs are compared with the corresponding bits in the slave address. the chip is selected if the com- pare is true. up to eight devices may be connected to the same bus by using different chip select bit combinations. these inputs must be connected to either v cc or v ss . for the sot-23 devices up to four devices may be con- nected to the same bus using different chip select bit combinations. in most applications, the chip address inputs a0, a1 and a2 are hard-wired to logic 0 or logic 1 . for applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic 0 or logic 1 before normal device operation can proceed. 2.2 serial data (sda) sda is a bidirectional pin used to transfer addresses and data into and out of the device. since it is an open- drain terminal, the sda bus requires a pull-up resistor to v cc (typical 10 k ? for 100 khz, 2 k ?? for 400 khz). for normal data transfer, sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. 2.3 serial clock (scl) the scl input is used to synchronize the data transfer from and to the device. 2.4 write-protect (wp) this pin must be connected to either v ss or v cc . if tied to v ss , write operations are enabled. if tied to v cc , write operations are inhibited but read operations are not affected. 3.0 functional description the 24aa014/24lc014 supports a bidirectional, 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as transmitter, while a device receiving data is defined as a receiver. the bus has to be controlled by a master device which gen- erates the serial clock (scl), controls the bus access and generates the start and stop conditions, while the 24aa014/24lc014 works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. name pdip soic tssop dfn (1) tdfn (1) msop sot-23 description a0 1 1 1 1 1 1 5 chip address input a1 2 2 2 2 2 2 4 chip address input a2 3 3 3 3 3 3 chip address input v ss 4444442g r o u n d sda 5 5 5 5 5 5 3 serial address/data i/o scl 6 6 6 6 6 6 1 serial clock wp 7 7 7 7 7 7 write-protect input v cc 8 8 8 8 8 8 6 +1.7v to 5.5v power supply note 1: the exposed pad on the dfn/tdfn packages can be connected to v ss or left floating. downloaded from: http:///
24aa014/24lc014 ds21809g-page 6 ? 2010 microchip technology inc. 4.0 bus characteristics the following bus protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined ( figure 4-1 ). 4.1 bus not busy (a) both data and clock lines remain high. 4.2 start data transfer (b) a high-to-low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 4.3 stop data transfer (c) a low-to-high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 4.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one bit of data per clock pulse. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is, theoretically, unlimited, though only the last sixteen will be stored when doing a write operation. when an over- write does occur, it will replace data in a first-in first-out fashion. 4.5 acknowledge each receiving device, when addressed, is required to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse, which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition ( figure 4-2 ). figure 4-1: data transfer sequence on the serial bus characteristics figure 4-2: acknowledge timing note: the 24aa014/24lc014 does not generate any acknowledge bits if an internal programming cycle is in progress. (a) (b) (c) (d) (a) (c) scl sda start condition address or acknowledge valid data allowed to change stop condition scl 9 8 7 6 5 4 3 2 1 123 transmitter must release the sda line at this point allowing the receiver to pull the sda line low to acknowledge the previous eight bits of data. receiver must release the sda line at this point so the transmitter can continue sending data. sda acknowledge bit data from transmitter data from transmitter downloaded from: http:///
? 2010 microchip technology inc. ds21809g-page 7 24aa014/24lc014 5.0 device addressing a control byte is the first byte received following the start condition from the master device ( figure 5-1 ). the control byte consists of a four-bit control code; for the 24aa014/24lc014 this is set as 1010 binary for read and write operations. the next three bits of the control byte are the chip select bits (a2, a1, a0). the chip select bits allow the use of up to eight 24aa014/ 24lc014 devices on the same bus and are used to select which device is accessed. the chip select bits in the control byte must correspond to the logic levels on the corresponding a2, a1 and a0 pins for the device to respond. these bits are in effect the three most significant bits of the word address. for the sot-23 package, the a2 address pin is not available. during device addressing, the a2 chip select bit should be set to 0 . the last bit of the control byte defines the operation to be performed. when set to a 1 , a read operation is selected. when set to a 0 , a write operation is selected. following the start condition, the 24aa014/ 24lc014 monitors the sda bus, checking the control byte being transmitted. upon receiving a 1010 code and appropriate chip select bits, the slave device out- puts an acknowledge signal on the sda line. depend- ing on the state of the r/w bit, the 24aa014/24lc014 will select a read or write operation. figure 5-1: control byte format 5.1 contiguous addressing across multiple devices the chip select bits a2, a1 and a0 can be used to expand the contiguous address space for up to 8k bits by adding up to eight 24aa014/24lc014 devices on the same bus. in this case, software can use a0 of the control byte as address bit a8, a1 as address bit a9, and a2 as address bit a10. it is not possible to sequentially read across device boundaries. for the sot-23 package, up to four 24aa014/24lc014 devices can be added for up to 4k bits of address space. in this case, software can use a0 of the control byte as address bit a8, and a1 as address bit a9. it is not possible to sequentially read across device bound- aries. 1010 a2 a1 a0 sa c k r/w control code chip select bits slave address acknowledge bit start bit read/write bit downloaded from: http:///
24aa014/24lc014 ds21809g-page 8 ? 2010 microchip technology inc. 6.0 write operations 6.1 byte write following the start signal from the master, the device code(4 bits), the chip select bits (3 bits) and the r/w bit (which is a logic low) are placed onto the bus by the master transmitter. the device will acknowledge this control byte during the ninth clock pulse. the next byte transmitted by the master is the word address and will be written into the address pointer of the 24aa014/ 24lc014. after receiving another acknowledge signal from the 24aa014/24lc014, the master device will transmit the data word to be written into the addressed memory location. the 24aa014/24lc014 acknowl- edges again and the master generates a stop condition. this initiates the internal write cycle and the 24aa014/24lc014 will not generate acknowledge signals during this time ( figure 6-1 ). if an attempt is made to write to the protected portion of the array when the hardware write protection has been enabled, the device will acknowledge the command, but no data will be written. the write cycle time must be observed even if write protection is enabled. 6.2 page write the write-control byte, word address and the first data byte are transmitted to the 24aa014/24lc014 in the same way as in a byte write. but instead of generating a stop condition, the master transmits up to 15 addi- tional data bytes to the 24aa014/24lc014 that are temporarily stored in the on-chip page buffer and will be written into the memory once the master has transmit- ted a stop condition. upon receipt of each word, the four lower order address pointer bits are internally incremented by one. the higher order four bits of the word address remain constant. if the master should transmit more than 16 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received, an inter- nal write cycle will begin ( figure 6-2 ). if an attempt is made to write to the protected portion of the array when the hardware write protection has been enabled, the device will acknowledge the command, but no data will be written. the write cycle time must be observed even if write protection is enabled. 6.3 write protection the wp pin must be tied to v cc or v ss . if tied to v cc , the entire array will be write-protected. if the wp pin is tied to v ss , write operations to all address locations are allowed. the wp pin is not available on the sot-23 package. figure 6-1: byte write note: page write operations are limited to writ- ing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or page size) and end at addresses that are integer multiples of [page size C 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. it is therefore necessary that the application software prevent page write operations that would attempt to cross a page boundary. s p bus activity master sda line bus activity st a r t st o p control byte word address data ac k ac k ac k downloaded from: http:///
? 2010 microchip technology inc. ds21809g-page 9 24aa014/24lc014 figure 6-2: page write s p bus activity master sda line bus activity st a r t control byte word address (n) data (n) data (n + 15) st o p ac k ac k ac k ac k ac k data (n +1) downloaded from: http:///
24aa014/24lc014 ds21809g-page 10 ? 2010 microchip technology inc. 7.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write command has been issued from the master, the device initiates the internally-timed write cycle and ack polling can be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w = 0 ). if the device is still busy with the write cycle, no ack will be returned. if no ack is returned, the start bit and control byte must be re-sent. if the cycle is complete, the device will return the ack and the master can then proceed with the next read or write command. see figure 7-1 for a flow diagram of this operation. figure 7-1: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0 )? next operation no yes downloaded from: http:///
? 2010 microchip technology inc. ds21809g-page 11 24aa014/24lc014 8.0 read operations read operations are initiated in the same way as write operations, with the exception that the r/w bit of the slave address is set to 1 . there are three basic types of read operations: current address read, random read and sequential read. 8.1 current address read the 24aa014/24lc014 contains an address counter that maintains the address of the last word accessed, internally incremented by one. therefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. upon receipt of the slave address with the r/w bit set to 1 , the 24aa014/24lc014 issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer, but does generate a stop condition and the 24aa014/24lc014 discontinues transmission ( figure 8-1 ). 8.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, the word address must first be set. this is done by sending the word address to the 24aa014/24lc014 as part of a write operation. once the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. the master then issues the control byte again but with the r/w bit set to a 1 . the 24aa014/24lc014 will then issue an acknowl- edge and transmits the eight-bit data word. the master will not acknowledge the transfer, but does generate a stop condition and the 24aa014/24lc014 discontin- ues transmission ( figure 8-2 ). after this command, the internal address counter will point to the address location following the one that was just read. 8.3 sequential read sequential reads are initiated in the same way as a random read except that after the 24aa014/24lc014 transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. this directs the 24aa014/24lc014 to transmit the next sequentially addressed 8-bit word ( figure 8-3 ). to provide sequential reads the 24aa014/24lc014 contains an internal address pointer which is incremented by one at the completion of each opera- tion. this address pointer allows the entire memory contents to be serially read during one operation. the internal address pointer will automatically roll over from address 07fh to address 000h. figure 8-1: current address read bus activity master sda line bus activity p s s t o p control byte s t a r t data a c k n o a c k downloaded from: http:///
24aa014/24lc014 ds21809g-page 12 ? 2010 microchip technology inc. figure 8-2: random read figure 8-3: sequential read s p s bus activity master sda line bus activity st a r t s t o p control byte a c k word address (n) control byte s t a r t data (n) a c k a c k n o a c k bus activity master sda line bus activity control byte data (n) data (n + 1) data (n + 2) data (n + x) no a c k ac k ac k ac k ac k s t o p p downloaded from: http:///
? 2010 microchip technology inc. ds21809g-page 13 24aa014/24lc014 9.0 packaging information 9.1 package marking information xxxxxxxx t/xxxnnn yyww 8-lead pdip (300 mil) example: 8-lead soic (3.90 mm) example: xxxxxxxt xxxxyyww nnn 8-lead tssop example: 24lc014 i/p 12f 0521 24lc014i sn 0521 12f 8-lead msop example: xxxx tyww nnn 4l14 i521 12f 4l14i 52112f xxxxt ywwnnn 3 e 3 e 8-lead 2x3 dfn example: 2n4 521 12 xxxyww nn 8-lead 2x3 tdfn example: an4 521 12 xxx yww nn downloaded from: http:///
24aa014/24lc014 ds21809g-page 14 ? 2010 microchip technology inc. part number 1st line marking codes tssop msop dfn tdfn sot-23 i-temp e-temp i-temp e-temp i-temp e-temp 24aa014 4a14 4a14t 2n1 an1 hjnn 24lc014 4l14 4l14t 2n4 2n5 an4 an5 hgnn hhnn note: t = temperature grade (i, e) 6-lead sot-23 xxnn hgec example: legend: xx...x part number or part number code t temperature (i, e) y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) note : for very small packages with no room for the pb-free jedec designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e note: please visit www.microchip.com/pbfree for the latest information on pb-free conversion. * standard otp marking consists of microchip part number, year code, week code, and traceabili ty code. downloaded from: http:///
? 2010 microchip technology inc. ds21809g-page 15 24aa014/24lc014 n e1 note 1 d 12 3 a a1 a2 l b1 b e e eb c downloaded from: http:///
24aa014/24lc014 ds21809g-page 16 ? 2010 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2010 microchip technology inc. ds21809g-page 17 24aa014/24lc014 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
24aa014/24lc014 ds21809g-page 18 ? 2010 microchip technology inc. downloaded from: http:///
? 2010 microchip technology inc. ds21809g-page 19 24aa014/24lc014 d n e e1 note 1 12 b e c a a1 a2 l1 l downloaded from: http:///
24aa014/24lc014 ds21809g-page 20 ? 2010 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2010 microchip technology inc. ds21809g-page 21 24aa014/24lc014 d n e e1 note 1 1 2 e b a a1 a2 c l1 l downloaded from: http:///
24aa014/24lc014 ds21809g-page 22 ? 2010 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2010 microchip technology inc. ds21809g-page 23 24aa014/24lc014 d n e note 1 1 2 exposed pad note 1 2 1 d2 k l e2 n e b a3 a1 a note 2 bottom view top view downloaded from: http:///
24aa014/24lc014 ds21809g-page 24 ? 2010 microchip technology inc. downloaded from: http:///
? 2010 microchip technology inc. ds21809g-page 25 24aa014/24lc014 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
24aa014/24lc014 ds21809g-page 26 ? 2010 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
? 2010 microchip technology inc. ds21809g-page 27 24aa014/24lc014 downloaded from: http:///
24aa014/24lc014 ds21809g-page 28 ? 2010 microchip technology inc. b e 4 n e1 pin1idby laser mark d 1 2 3 e e1 a a1 a2 c l l1 downloaded from: http:///
? 2010 microchip technology inc. ds21809g-page 29 24aa014/24lc014 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:///
24aa014/24lc014 ds21809g-page 30 ? 2010 microchip technology inc. appendix a: revision history revision b corrections to section 1.0, electrical characteristics. revision c added dfn package. revision d (10/2007) add pb-free to features; revise section 8.3; replace package drawings; update product id system. revision e (04/2008) replaced package drawings; added tdfn package; revised product id section. revision f (10/2009) added 6-lead sot-23 package; removed pin function table; revised section 2.0; revised section 6.3. revision g (08/2010) revised device selection table; added automotive temp; revised tables 1-1, 1-2, figure 1-1, package marking drawings and product id system. downloaded from: http:///
? 2010 microchip technology inc. ds21809g-page 31 24aa014/24lc014 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com , click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com downloaded from: http:///
24aa014/24lc014 ds21809g-page 32 ? 2010 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in whic h our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this docume nt. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21809g 24aa014/24lc014 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? downloaded from: http:///
? 2010 microchip technology inc. ds21809g-page 33 24aa014/24lc014 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: 24aa014: 1.7v, 1 kbit addressable serial eeprom 24aa014t: 1.7v, 1 kbit addressable serial eeprom (tape and reel) 24lc014: 2.5v, 1 kbit addressable serial eeprom 24lc014t: 2.5v, 1 kbit addressable serial eeprom (tape and reel) temperature range: i = -40c to +85c e = -40c to +125c package: ot = plastic small outline (sot-23), (tape & reel only), 6-lead p = plastic dip, (300 mil body), 8-lead sn = plastic soic, (3.90 mm body) st = tssop, 8-lead ms = msop, 8-lead mc = 2x3 dfn, 8-lead mny (1) = plastic dual flat (tdfn), no lead package, 2x3 mm body, 8-lead (tape & reel only) part no. x /xx package temperature range device examples: a) 24aa014-i/p: industrial temperature, 1.7v, pdip package. b) 24aa014-i/sn: industrial temperature, 1.7v, soic package. c) 24aa014t-i/st: industrial temperature, 1.7v, tssop package, tape and reel. a) 24lc014-i/p: industrial temperature, 2.5v, pdip package. b) 24lc014t-i/sn: industrial temperature, 2.5v, soic package, tape and reel. c) 24lc014t-i/ms: industrial temperature, 2.5v, msop package, tape and reel. a) 24lc014t-e/mny: automotive tempera- ture, 2.5v, tdfn package, tape and reel. b) 24lc014-e/ms: automotive tempera- ture, 2.5v, msop package. note 1: y indicates a nickel, palladium, gold (nipdau) finish. downloaded from: http:///
24aa014/24lc014 ds21809g-page 34 ? 2010 microchip technology inc. notes: downloaded from: http:///
? 2010 microchip technology inc. ds21809g-page 35 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, octopus, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2010, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-60932-464-3 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. downloaded from: http:///
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